General Information

Course Modules

Concepts: Software and Hardware Processes for Embedded Systems

01 – Introduction

04 – Synchronization, Communication and Mutual Exclusion

05 – A Closer Look at Synchronization and Scheduling Methods

No slides, please refer to scans of lecture notes (LN…) and diagrams.

Please read Chapters 1-4 of ESF (Embedded Systems Fundamentals, FRDM-KL25Z, 1st edition) by 9/12/25. It will help with THW2.

Starting Point: A Non-Preemptive Task Scheduler

06 – Schedulers and Basic Response Time Analysis, Scheduler Wish List

07 – Building a Run-To-Completion Scheduler

ESF Chapter 4: Arm Cortex-M0+ Processor Core and Interrupts

ESF Chapter 7. Timers

08 – Using the RTCS for Two Basic Examples

ESF Chapter 3: Basics of Software Concurrency

Implementing Applications using Platform 1: Hardware Peripherals, Interrupts and Non-Preemptive Tasks

09 – Application Design Process with RTC Scheduler & Interrupts (Platform 1)

10 – Example Applications on RTC Scheduler

10 Example Apps on RTCS v5

ESF Readings

  • Chapter 6: Analog Interfacing
  • Chapter 7: Timers
  • Chapter 8: Serial Communications

Note: information on peripherals used in the applications (reading assignments, slides) has been moved to this page: Reference Information for Example Applications

A Closer Look at Response Time Analysis and I/O-Driven Synchronization Requirements

11 – Response Time Analysis Concepts for Multitasking Software

12 – I/O-Driven Synchronization in Example Applications

Meeting Performance Challenges with Platform 1

13a – Challenges: Overview

Overview of Application Challenges

13 App Perf v2

13b – Waveform Generator: Stabilizing Ouput Timing (part 1)

(14, 15 – Review and Midterm Exam)

17 – WaveGen: Loosening Processing Deadlines, Interfering Less

18 – Scope: Synchronizing Better with Input Events, Safely Sharing Resources, Stabilizing Input Timing, Interfering Less

19b, 20 – Constant-Current LED Driver: Control System with Synchronous Sampling

Implementing Applications with Platform 2: Hardware Peripherals, Interrupts and RTOS with Preemptive Tasks

Task Preemption and Resumption

21 – Supporting Task Preemption and Resumption

RTXv5: Real-Time Operating System Features and Services

21-22 – Concepts, Threads and Delays
22-24 – Synchronization

22- Event Flags

Please read this brief summary of the issues involved

Please read pages 1 through 6 (Introduction)

23 – Semaphores

Please read pages 7 through 15 ((Semaphores, Signaling, Rendezvous)

23 – Mutexes

Please read pages 15 through 19 ((Mutex)

24 – Communication

Using RTOS (and Hardware) for Application Challenges

2x_Overview of Sync. and Comm. Challenges in Shield and Project (slides)

Challenge: Waveform Generator: Balancing Responsiveness and Timing Interference

Challenge: Sharing the LCD Safely but Promptly

Challenge: Sharing the ADC With Demanding Input Timing and Without a Mutex

Advanced RTOS Topics

Meeting Performance Challenges with Platform 2

  • Stabilizing input and output timing
  • Synchronizing better with input events
  • Safely sharing resources (data and hardware)
  • Loosening processing deadlines, tolerating timing mismatches
  • Reducing timing interference to other processes
  • Reducing overhead through batch processing

Improving the Embedded System Development Process

  • Development process model
  • Design before coding
  • Graphical design representations for embedded systems with UML
  • Requirements, testability, traceability
  • Peer review, testing, static analysis
  • Debugging

Creating Dependable Systems

  • Development Process
  • Technical Methods
    • Hardware
    • Software

Toolbox Topics

These topics are presented throughout the course as appropriate. You might think of them as problem-solving tools in your toolbox.

  • Basic Hardware Features
    • Interfacing
      • Simple digital signals
      • Analog signals
      • Timed digital signals (PWM, PFM, etc.)
      • Communications
        • Parallel bus
        • Serial: SPI, async. serial, I2C, CAN
    • More Peripherals
      • Timing support
      • Dependability
      • Others
  • Advanced Hardware Features
    • Peripheral Enhancements and Upgrades
    • Direct Memory Access Controller
    • Peripheral Interconnect
    • Hardware FSMs
    • Programmable Logic

Solutions

Homework Solutions

Are T1’s read and use of pos a critical section? Probably yes — it’s a challenging problem:

Other Information